The explosive growth of cellular phone industry and the ever increasing and continual integration of Bluetooth, Global Positioning System (GPS) and Wireless LAN (WLAN) with cellular phones demand a low cost as well as area-efficient design for the various components. While the known continual scaling down of CMOS transistor with process node migration can significantly reduce the area of the digital content of these systems, it is noted however that the analog portion, primarily in the radio, does not lend itself to scaling down as much. An all-digital PLL (ADPLL-All Digital Phase Locked Loop) referred to recently in the IEEE journal of Solid State Circuits (vide: R. B. Staszewski and C.-M. Hung and N. Barton and M.-C. Lee and D. Leipold, “A Digitally Controlled Oscillator in a 90 nm Digital CMOS process for Mobile Phones, IEEE Journal of Solid State Circuits, pp. 2203-2211, November 2005) enables replacement of the conventional analog PLL in the radios. This in turn facilitates the design of a radio with a significantly more digital logic than earlier possible and hence can scale down with process node. Such digital architecture for radio design is referred to herein as Digital Radio Processor (DRP).
The ADPLL is at the core of DRP design and implements the PLL completely in digital domain. The idea in DRP is to use the accuracy of timing in edge transitions of digital signals rather than the voltage levels of the analog signals. Hence, analogous to voltage controlled oscillator (VCO), a digitally controlled oscillator (DCO) is used in ADPLL.
A polar architecture is used in a DRP to reuse the ADPLL for modulation, thereby reducing area. The DRP includes a Cordic block which converts I, Q samples from baseband to r, θ samples. For purposes of this invention, the phase difference between consecutive samples is termed the frequency control word (FCW). It is noted that the consecutive samples in embodiments are reckoned at the Cordic output. In the transmitter, RF modulation is performed in the digital domain by feeding FCW into the ADPLL. This in turn requires the DCO to provide the frequency range for modulation known as the modulation range of the DCO. The DCO also needs to tune to operating channel center frequencies of the system, and herein, the frequency range required to support this tuning is known as the tuning range of the DCO.
For the Cordic block, the Cordic rate (say, fs) increases significantly as the bandwidth of the modulation range and its EVM (Error Vector Magnitude) requirement increase. It is noted that large phase changes occur as the r, θ trajectory crosses the origin. For example, a phase change of ±π occurring near the origin causes the FCW range to be ±fs/2 which is the same as the Cordic rate, namely fs. This implies the modulation range of the DCO to be the same as the Cordic rate, which for example is 300 MHz for WLAN applications.
It is further noted that the DCO also needs to provide I and Q phases for the receiver, which is accomplished by operating the DCO at twice the carrier frequency. For example, at the receiver, to support WLAN in 4.8-5.9 GHz band, the tuning range of the DCO should be 9.6-11.8 GHz. It is also noted that the ISM band of 2.4 GHz band can also be catered to with the same DCO by dividing the frequency by 4. For example, for the transmitter to support a modulation range of 300 MHz (Cordic rate) in 2.4 GHz band, the DCO modulation range should be 1.2 GHz at 11.8 GHz. One disadvantage with the above provision is that the higher modulation range increases parasitic capacitance and makes it difficult to provide the large tuning range. The other disadvantage is that the number of capacitors needs to be increased in order to provide the higher modulation range, and these capacitors are very sensitive to the supply voltage variations. Consequently the system becomes sensitive to high transmitting powers and causes severe EVM degradation during transmission.
An exemplary form of transmitter architecture for a DRP is shown in FIG. 1. It is seen that in-phase (I) and quadrature (Q) signals coming from baseband are converted into amplitude(r) and phase (θ) by the Cordic block before being processed in the radio. The advantage of the polar architecture is that the r and θ samples are digitally processed separately before being finally mixed in a Digital Power Amplifier (DPA). In the phase path, the phase difference known as frequency control word (FCW) is used in the processing. In fact, modulation is also performed in digital domain by feeding in FCW directly into the DCO. The DCO can be modeled as an accumulator of frequency to trace the phase trajectory or, alternatively, to cause linear interpolation between two phase instants. Unlike a VCO, the output of DCO is a square wave. The modulation information is captured in the transition edges of the DCO clock. As a result of this, when transmitting, the clock output of DCO is data modulated and is of non-uniform period, and not a constant uniform clock. This digital modulation scheme imposes certain constraints on the DCO and system as described next.
The function of Cordic block as aforesaid is to capture the I and Q signal trajectory in terms of r and θ. This implies that as the signal trajectory passes through origin from 1st quadrant to 3rd quadrant, or 2nd quadrant to 4th quadrant or vice-versa, there can be an instantaneous phase change close to ±π radians. If the sampling frequency of the Cordic is fCORDIC then the instantaneous frequency change is
                    ±        π                    2        ⁢        π              *          f      CORDIC        =            ±              f        CORDIC              /    2.  As this FCW is fed directly into the DCO it should be able to support these instantaneous frequency requirements. This frequency range requirement coming due to modulation is called the modulation range of the DCO. From the above discussion it is evident that the modulation range of DCO should be fCORDIC.
If the modulation bandwidths are quite small like in GSM, Bluetooth or WCDMA then sampling frequency of Cordic is small and hence a small modulation range is required for DCO. However as the modulation bandwidth goes up the sampling frequency of the Cordic increases considerably. For instance, to support the WLAN signal the sampling frequency of the Cordic and the DCO modulation range should be 300 MHz.
Wireless LAN systems operate in 2.4 GHz(ISM band) as well as 4.8-5.9 GHz (including 802.11j and UNII band). This implies that DCO should be able to tune to any of the center frequencies in the above bands. This center frequency tuning requirement is referred to as DCO tuning range. Also note that though the transmitter in DRP has polar architecture, the receiver has a conventional architecture of in-phase (I) and quadrature (Q) signals. Therefore, at a particular carrier frequency the system needs cosine and sine waveforms. This is accomplished by operating the DCO at twice the carrier frequency for UNII band and four times the carrier frequency in ISM band. These requirements imply that in order to support WLAN, DCO should have tuning range of 9.6-11.8 GHz. The modulation range requirement of 300 MHz at 2.4 GHz translates to 1.2 GHz modulation range at 9.6 GHz.
The modulation and tuning range of a DCO are very critical parameters in its design. As the modulation range of DCO increases, the number of capacitors required in the design also increases thereby increasing the parasitic capacitance. This parasitic capacitance makes it difficult to achieve wide tuning range while providing the large modulation range for the DCO. An added disadvantage is that these capacitors are very sensitive to supply-voltage fluctuations. Therefore, the larger the number of capacitors in the DCO the greater is their supply voltage sensitivity. This makes it extremely difficult to design a DCO with 1.2 GHz modulation range and tuning range from 9.6-11.8 GHz. The tuning range cannot be reduced as it is decided by operating channel frequencies. Consequently the modulation range requirement of the DCO should be reduced to make the DCO design feasible.
Prior Art: Exception Handling:
One prior art method of reducing modulation range is to generate merely 0°, 90°, 180°, etc., phases at the DCO output. Considering that the large phase jumps of 180°, 90° do not occur frequently, the large phase jumps can be treated as exceptions, and the DCO phase changed accordingly. Even though exception handling (which is used for example in DRP for WCDMA) is acceptable and produces about the same EVM as the full modulation DCO, it is noted that the method of exception handling (i) does not trade off the EVM to get reduced out of band noise, and (ii) does not use the information that for large jumps, the amplitude r is small, and gradual deviation from deal trajectory will not affect EVM considerably.
Also, with prior art, phase noise is degraded and the complexity increases when more phases of the DCO clock are needed such as 22 ½°, 45°, etc, when the angle is not 180/2n where n is an integer.
It is noted that in prior art, the exception handling technique has been used to address the sudden phase jumps of ±π or ±π/2 radians. Thus the instantaneous large phase jumps were avoided thereby avoiding the high DCO modulation range requirement. As an example, for a phase jump of π, instead of feeding a FCW of π, zero was fed into the DCO and its clock was inverted to accommodate the π jump. Exception handling works well for single-carrier systems since it maintains the error vector magnitude (EVM) as with a full modulation range DCO. However it has the disadvantage that it significantly raises the out of band noise floor for OFDM systems. It also has high complexity as it is implemented in the analog domain by multiplexing the different phases of DCO clock and hence can also potentially degrade the phase noise performance of the system. Furthermore, the complexity increases as more phases of DCO clock like π/4, π/8 etc. are needed or when the angle is not of the form π/2n, where n is an integer. For example, one method to generate π/4 phase is to run the DCO at 8 times the carrier frequency (2.4 GHz) and then use dividers to divide it down to get the various phases. But for carrier frequency of 2.4 GHz it is extremely difficult for the DCO to operate at 19.2 GHz. Furthermore, if the dividers are operating at these high speeds, the consequent power consumption also increases significantly which is very significant for systems which are integrated with cellular phones.